A
Anonymous
Guest
Hi
To avoid having to do log arithmetic on a PIC uC (latency issues) would an antilog amp give a near enough linear ground signal???
If so, the arithmetic would simplify to V = -tx + k
where V is signal amplitude, t is sample time, x is the initial sample time divided by a latter, and k is the first sample amplitude.
After two samples, a 3rd can be predicted. If it fits within a pre-determined window then only ground components are being detected.
Another point. The samples would be held on integrating sample and hold amps. Would a sample width of 5uS be sufficient to achieve a good s/n ratio. I guess that's like asking how long is a piece of string when you can't see my integrator design.
Cheers
Kev.
To avoid having to do log arithmetic on a PIC uC (latency issues) would an antilog amp give a near enough linear ground signal???
If so, the arithmetic would simplify to V = -tx + k
where V is signal amplitude, t is sample time, x is the initial sample time divided by a latter, and k is the first sample amplitude.
After two samples, a 3rd can be predicted. If it fits within a pre-determined window then only ground components are being detected.
Another point. The samples would be held on integrating sample and hold amps. Would a sample width of 5uS be sufficient to achieve a good s/n ratio. I guess that's like asking how long is a piece of string when you can't see my integrator design.
Cheers
Kev.