In doing my research and reading all relevant posts on this and the Geoquest Forum I have come to some fundamental design limits understanding. I am looking to know the ranges of design limit parameters in the following areas that I can optimize. Those who have many years of PI design and building experience must have thought of these issues and more importantly, have resolved them.
I decided to start simple with the mono coil on the Hammerhead PI before doing the DD coil configuration.
Being a retired Technical Writer from the U.S. Army (Communications-Electronics Command) makes me want to decompose this project into what I perceive as the critical building blocks. I am just starting with the coil while I assemble the circuit board components and do research.
Are my assumptions below correct?
1. Total capacitance determines the coils ringing frequency. More capacitance stores more energy and causes that ringing frequency to be lower thus making the delay between the tail end of the transmit (TX) pulse and the receive (RX) window longer. This is undesireable for low conductivity items like thin gold rings. The items below all affect total capacitance.
2. The energy in the coil affects the minimal possible time it takes for the coil ringing to settle. High resistance coils or coils with a series resistor have the potential to be dampened quicker.
3. The MOSFET driving the coil contributes a few hundred PFs to the total capacitance. I suspect that little can be done to improve things here other than good layout and good lead dressing. While it may be possible to find a MOSFET with lower capacitance, I suspect the MOSFET is not a major contributor to the total capacitance.
4. The coil cable can contribute up to about 100 pf to the total capacitance, so low capacitance cable should be used. A quick check of the wire catalogs show that the range is a low of 10 pf/foot to a high of 30 pf/foot. Finding something that is flexible and a practical diameter puts the most likely cable candidate in the 19.5/foot PF range. Little other optimization with the coil cable seems practicle.
5. The coil itself will contain anywhere from about 60 feet to about 80 feet of wire depending on the diameter and recommended design targets. More turns produce a larger tramsmit field as well as make the receive mode signal more sensitive. Fewer turms makes the coil faster with lower capacitance. In using regular stranded hook up wire, I measure 19pf/foot. I suspect this measurement is only valid for a spiral wound coil where the wire is not bunched together. My coil is 67 feet long, 10.25", 25 turns, 395 uH and would have a minimum of 1273 pf if wound in a spiral. But since it is bunched together in a .25" round bundle, I suspect it has at least double the capacitance, if not more. The only way to reduce capicitance further is to get creative with some kind of basket wound coil or use wire with thicker insulation. The net effect is to increase the spacing between turns to reduce the total capacitance at the expense of incresing the bulk of the coil. Eric, Reg and others have recommended a coil target of between 200 uH and 400 uH in various posts. I can remove 3 turns and bring the coil inductance down to 300 uH, but I suspect this will have a minimal effect as there are other more influencing total capititance drivers. Is this true?
6. A shield is necessary at delays below about 15 uS. However there is a side effect that it adds capacitance. My aluminum tape shield adds 670 pf between the shield and one leg of the coil. I suspect that this also increases the distributed capacitance of the coil and increases the total capacitance. The only optimization I have seen is the recommendation to increase the spacing between the coil and the shield by using plastic spiral wrap under the foil tape. I only had room to wind two layers of electrical tape over the wire and still have the final coil fit in to the housing. Is it safe to assume that using a spiral wrap would decrease the distributed capacitance of the shield to about half?
7. The damping resistor value is critical for optimizing the coil to the PI electronics. From forum posts I have read that reducing total capacatance allows the use of a larger resistor to achieve critical damping. This initially seemed counter intuitive but make sense in that the capacitive resoviour (total capactiance)is smaller and requires less damping (a higher resistor value) to achieve critical damping. What is the typical ringing frequencies when coils are in the 10, 12 and 15u delay limits? How does removing a coil turn affect the value of the damping resistor? I am just trying to determine how sensitive the value of the damping resistor is to those variables that I can easily control. Can critical damping be determined in a functioning PI machine without a scope? I suspect that placing a small pot in place of the damping resistor (temporary), setting it initially near a target value of 500 to 600 ohms, will allow some tweaking of the other Hammerhead PI controls to achieve a close approximation of critical damping. Please explain if this is possible? What are the typical damping resistor values for coils that are 200 uH, 300 uH, 400 uH and 500 uH? I have seen damping resistors as low as 100 ohms and as high as 680 ohms. I suspect that the value of the critical damping resistor reflects something significant about the total system capacitance, coil design, or design of the PI coil pulse stream. Can you expand on this? What is the minimal bandwidth scope that can see the critical damping?
I have read all posts related to coils and have synthesized my underestand above. I pose these questions to help further my understanding of PI design paramenters and optimization limits. I suspect that others will also benefit from your expertise in this rare opportunity to have a dialog with you.
Thanks for your time and expertise.
bbsailor
